Timing Messages

Report Title	Timing Analysis Report
Design File	/home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/impl/gwsynthesis/gao_hdmi_color.vg
Physical Constraints File	/home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/gao_hdmi_color.cst
Timing Constraint File	/home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/time.sdc
Tool Version	V1.9.11
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Thu Jun 26 10:23:52 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	449
Numbers of Endpoints Analyzed	215
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	28

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk_osc	Base	37.037	27.000	0.000	18.518			clk
2	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	Generated	6.006	166.500	0.000	3.003	clk_ibuf/I	clk_osc	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
3	Gowin_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Generated	6.006	166.500	0.000	3.003	clk_ibuf/I	clk_osc	Gowin_PLLVR_inst/pllvr_inst/CLKOUTP
4	Gowin_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Generated	12.012	83.250	0.000	6.006	clk_ibuf/I	clk_osc	Gowin_PLLVR_inst/pllvr_inst/CLKOUTD
5	Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Generated	18.018	55.500	0.000	9.009	clk_ibuf/I	clk_osc	Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3
6	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	Generated	30.030	33.300	0.000	15.015	Gowin_PLLVR_inst/pllvr_inst/CLKOUT	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_div_5/clkdiv_inst/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	166.500(MHz)	173.500(MHz)	2	TOP
2	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	33.300(MHz)	83.152(MHz)	7	TOP

No timing paths to get frequency of clk_osc!

No timing paths to get frequency of Gowin_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of Gowin_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk_osc	Setup	0.000	0
clk_osc	Hold	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	Setup	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	Hold	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0
u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	Setup	0.000	0
u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.242	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_0_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[3].oddr_inst/D1	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	5.719
2	0.978	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_0_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[3].oddr_inst/D0	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	4.983
3	1.237	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	4.369
4	1.295	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	4.311
5	1.295	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	4.311
6	1.478	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	4.128
7	1.478	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_1_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	4.128
8	1.481	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[0].oddr_inst/D0	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	4.480
9	1.537	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[0].oddr_inst/D1	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	4.424
10	1.674	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.932
11	1.674	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_3_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.932
12	1.778	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_0_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[2].oddr_inst/D1	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	4.183
13	1.803	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[1].oddr_inst/D1	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	4.158
14	1.981	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.625
15	1.981	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.625
16	1.981	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.625
17	1.999	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.607
18	1.999	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.607
19	1.999	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_1_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.607
20	2.040	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[1].oddr_inst/D0	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.921
21	2.172	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.434
22	2.172	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.434
23	2.172	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.434
24	2.184	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_0_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[2].oddr_inst/D0	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.777
25	2.304	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0/D	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	6.006	0.000	3.302

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-0.715	u_dvi_encoder/encb/dout_6_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.260
2	-0.715	u_dvi_encoder/encb/dout_6_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.260
3	-0.676	u_dvi_encoder/encb/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.299
4	-0.676	u_dvi_encoder/encb/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.299
5	-0.492	u_dvi_encoder/encg/dout_9_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.482
6	-0.492	u_dvi_encoder/encr/dout_8_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.482
7	-0.492	u_dvi_encoder/encr/dout_9_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.482
8	-0.490	u_dvi_encoder/encb/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.485
9	-0.490	u_dvi_encoder/encb/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.485
10	-0.473	u_dvi_encoder/encb/dout_9_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.501
11	-0.473	u_dvi_encoder/encb/dout_8_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.501
12	-0.469	u_dvi_encoder/encr/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.505
13	-0.469	u_dvi_encoder/encr/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.505
14	-0.469	u_dvi_encoder/encr/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.505
15	-0.422	u_dvi_encoder/encg/dout_8_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.552
16	-0.365	u_dvi_encoder/encb/dout_6_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_1_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.610
17	-0.342	u_dvi_encoder/encg/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.632
18	-0.339	u_dvi_encoder/encg/dout_6_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_2_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.635
19	-0.339	u_dvi_encoder/encg/dout_6_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.635
20	-0.337	u_dvi_encoder/encg/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_2_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.638
21	-0.337	u_dvi_encoder/encg/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.638
22	-0.337	u_dvi_encoder/encg/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.638
23	-0.320	u_dvi_encoder/encb/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.655
24	-0.250	u_dvi_encoder/encg/dout_7_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.725
25	-0.250	u_dvi_encoder/encr/dout_6_s0/Q	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.945	1.725

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	1.675	2.925	1.250	Low Pulse Width	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0
2	1.675	2.925	1.250	Low Pulse Width	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0
3	1.675	2.925	1.250	Low Pulse Width	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0
4	1.675	2.925	1.250	Low Pulse Width	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_0_s0
5	1.675	2.925	1.250	Low Pulse Width	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
6	1.675	2.925	1.250	Low Pulse Width	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_2_s1
7	1.675	2.925	1.250	Low Pulse Width	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_3_s1
8	1.675	2.925	1.250	Low Pulse Width	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_0_s0
9	1.675	2.925	1.250	Low Pulse Width	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_2_s0
10	1.675	2.925	1.250	Low Pulse Width	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_0_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.242
Data Arrival Time	8.236
Data Required Time	8.478
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_0_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[3].oddr_inst
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C30[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_0_s0/CLK
2.975	0.458	tC2Q	RF	2	R11C30[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_0_s0/Q
4.117	1.142	tNET	FF	1	R9C26[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n143_s2/I0
5.149	1.032	tINS	FF	1	R9C26[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n143_s2/F
8.236	3.086	tNET	FF	1	IOT4[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[3].oddr_inst/D1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	IOT4[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[3].oddr_inst/CLK
8.478	-0.045	tSu		1	IOT4[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[3].oddr_inst

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.032, 18.046%; route: 4.228, 73.939%; tC2Q: 0.458, 8.015%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path2

Path Summary:

Slack	0.978
Data Arrival Time	7.500
Data Required Time	8.478
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_0_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[3].oddr_inst
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R9C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_0_s0/CLK
2.975	0.458	tC2Q	RF	2	R9C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_0_s0/Q
3.314	0.339	tNET	FF	1	R9C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n147_s2/I0
4.413	1.099	tINS	FF	1	R9C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n147_s2/F
7.500	3.086	tNET	FF	1	IOT4[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[3].oddr_inst/D0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	IOT4[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[3].oddr_inst/CLK
8.478	-0.045	tSu		1	IOT4[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[3].oddr_inst

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.099, 22.056%; route: 3.425, 68.746%; tC2Q: 0.458, 9.198%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path3

Path Summary:

Slack	1.237
Data Arrival Time	6.886
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.787	1.325	tNET	FF	1	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n73_s0/I2
6.886	1.099	tINS	FF	1	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n73_s0/F
6.886	0.000	tNET	FF	1	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0/CLK
8.123	-0.400	tSu		1	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.198, 50.310%; route: 1.713, 39.199%; tC2Q: 0.458, 10.491%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path4

Path Summary:

Slack	1.295
Data Arrival Time	6.828
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.796	1.334	tNET	FF	1	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n68_s0/I2
6.828	1.032	tINS	FF	1	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n68_s0/F
6.828	0.000	tNET	FF	1	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0/CLK
8.123	-0.400	tSu		1	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.131, 49.431%; route: 1.722, 39.937%; tC2Q: 0.458, 10.632%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path5

Path Summary:

Slack	1.295
Data Arrival Time	6.828
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.796	1.334	tNET	FF	1	R12C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n67_s0/I2
6.828	1.032	tINS	FF	1	R12C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n67_s0/F
6.828	0.000	tNET	FF	1	R12C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R12C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0/CLK
8.123	-0.400	tSu		1	R12C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 2.131, 49.431%; route: 1.722, 39.937%; tC2Q: 0.458, 10.632%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path6

Path Summary:

Slack	1.478
Data Arrival Time	6.645
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.823	1.361	tNET	FF	1	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/n63_s0/I2
6.645	0.822	tINS	FF	1	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/n63_s0/F
6.645	0.000	tNET	FF	1	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0/CLK
8.123	-0.400	tSu		1	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.921, 46.534%; route: 1.749, 42.364%; tC2Q: 0.458, 11.103%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path7

Path Summary:

Slack	1.478
Data Arrival Time	6.645
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_1_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.823	1.361	tNET	FF	1	R12C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n62_s0/I2
6.645	0.822	tINS	FF	1	R12C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n62_s0/F
6.645	0.000	tNET	FF	1	R12C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R12C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_1_s0/CLK
8.123	-0.400	tSu		1	R12C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.921, 46.534%; route: 1.749, 42.364%; tC2Q: 0.458, 11.103%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path8

Path Summary:

Slack	1.481
Data Arrival Time	6.997
Data Required Time	8.478
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[0].oddr_inst
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0/CLK
2.975	0.458	tC2Q	RF	2	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0/Q
4.439	1.463	tNET	FF	1	R15C22[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n150_s2/I0
5.538	1.099	tINS	FF	1	R15C22[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n150_s2/F
6.997	1.459	tNET	FF	1	IOB22[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[0].oddr_inst/D0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	IOB22[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[0].oddr_inst/CLK
8.478	-0.045	tSu		1	IOB22[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[0].oddr_inst

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.099, 24.532%; route: 2.923, 65.237%; tC2Q: 0.458, 10.231%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path9

Path Summary:

Slack	1.537
Data Arrival Time	6.941
Data Required Time	8.478
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[0].oddr_inst
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0/CLK
2.975	0.458	tC2Q	RF	2	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0/Q
4.439	1.463	tNET	FF	1	R15C22[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n146_s2/I0
5.471	1.032	tINS	FF	1	R15C22[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n146_s2/F
6.941	1.470	tNET	FF	1	IOB22[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[0].oddr_inst/D1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	IOB22[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[0].oddr_inst/CLK
8.478	-0.045	tSu		1	IOB22[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[0].oddr_inst

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.032, 23.329%; route: 2.933, 66.310%; tC2Q: 0.458, 10.361%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path10

Path Summary:

Slack	1.674
Data Arrival Time	6.449
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.823	1.361	tNET	FF	1	R12C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n66_s0/I2
6.449	0.626	tINS	FF	1	R12C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n66_s0/F
6.449	0.000	tNET	FF	1	R12C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R12C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0/CLK
8.123	-0.400	tSu		1	R12C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.725, 43.869%; route: 1.749, 44.475%; tC2Q: 0.458, 11.656%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path11

Path Summary:

Slack	1.674
Data Arrival Time	6.449
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_3_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.823	1.361	tNET	FF	1	R12C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n65_s0/I2
6.449	0.626	tINS	FF	1	R12C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n65_s0/F
6.449	0.000	tNET	FF	1	R12C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R12C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_3_s0/CLK
8.123	-0.400	tSu		1	R12C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.725, 43.869%; route: 1.749, 44.475%; tC2Q: 0.458, 11.656%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path12

Path Summary:

Slack	1.778
Data Arrival Time	6.700
Data Required Time	8.478
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_0_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[2].oddr_inst
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C28[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_0_s0/CLK
2.975	0.458	tC2Q	RR	2	R11C28[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_0_s0/Q
3.395	0.420	tNET	RR	1	R12C28[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n144_s2/I0
4.427	1.032	tINS	RF	1	R12C28[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n144_s2/F
6.700	2.273	tNET	FF	1	IOB16[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[2].oddr_inst/D1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	IOB16[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[2].oddr_inst/CLK
8.478	-0.045	tSu		1	IOB16[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[2].oddr_inst

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.032, 24.670%; route: 2.693, 64.374%; tC2Q: 0.458, 10.956%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path13

Path Summary:

Slack	1.803
Data Arrival Time	6.675
Data Required Time	8.478
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[1].oddr_inst
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0/CLK
2.975	0.458	tC2Q	RF	2	R11C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0/Q
4.437	1.462	tNET	FF	1	R11C22[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n145_s2/I0
5.536	1.099	tINS	FF	1	R11C22[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n145_s2/F
6.675	1.139	tNET	FF	1	IOB22[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[1].oddr_inst/D1

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	IOB22[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[1].oddr_inst/CLK
8.478	-0.045	tSu		1	IOB22[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[1].oddr_inst

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.099, 26.429%; route: 2.601, 62.549%; tC2Q: 0.458, 11.022%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path14

Path Summary:

Slack	1.981
Data Arrival Time	6.142
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.320	0.858	tNET	FF	1	R11C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n87_s0/I2
6.142	0.822	tINS	FF	1	R11C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n87_s0/F
6.142	0.000	tNET	FF	1	R11C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R11C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/CLK
8.123	-0.400	tSu		1	R11C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.921, 52.987%; route: 1.246, 34.371%; tC2Q: 0.458, 12.642%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path15

Path Summary:

Slack	1.981
Data Arrival Time	6.142
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.320	0.858	tNET	FF	1	R11C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n86_s0/I2
6.142	0.822	tINS	FF	1	R11C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n86_s0/F
6.142	0.000	tNET	FF	1	R11C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R11C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/CLK
8.123	-0.400	tSu		1	R11C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.921, 52.987%; route: 1.246, 34.371%; tC2Q: 0.458, 12.642%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path16

Path Summary:

Slack	1.981
Data Arrival Time	6.142
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.320	0.858	tNET	FF	1	R11C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n85_s0/I2
6.142	0.822	tINS	FF	1	R11C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n85_s0/F
6.142	0.000	tNET	FF	1	R11C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R11C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0/CLK
8.123	-0.400	tSu		1	R11C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.921, 52.987%; route: 1.246, 34.371%; tC2Q: 0.458, 12.642%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path17

Path Summary:

Slack	1.999
Data Arrival Time	6.124
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.302	0.840	tNET	FF	1	R12C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n60_s0/I2
6.124	0.822	tINS	FF	1	R12C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n60_s0/F
6.124	0.000	tNET	FF	1	R12C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R12C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0/CLK
8.123	-0.400	tSu		1	R12C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.921, 53.252%; route: 1.228, 34.042%; tC2Q: 0.458, 12.706%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path18

Path Summary:

Slack	1.999
Data Arrival Time	6.124
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.302	0.840	tNET	FF	1	R12C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n61_s0/I2
6.124	0.822	tINS	FF	1	R12C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n61_s0/F
6.124	0.000	tNET	FF	1	R12C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R12C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0/CLK
8.123	-0.400	tSu		1	R12C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.921, 53.252%; route: 1.228, 34.042%; tC2Q: 0.458, 12.706%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path19

Path Summary:

Slack	1.999
Data Arrival Time	6.124
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_1_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.302	0.840	tNET	FF	1	R12C27[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n72_s0/I2
6.124	0.822	tINS	FF	1	R12C27[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n72_s0/F
6.124	0.000	tNET	FF	1	R12C27[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R12C27[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_1_s0/CLK
8.123	-0.400	tSu		1	R12C27[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.921, 53.252%; route: 1.228, 34.042%; tC2Q: 0.458, 12.706%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path20

Path Summary:

Slack	2.040
Data Arrival Time	6.438
Data Required Time	8.478
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[1].oddr_inst
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0/CLK
2.975	0.458	tC2Q	RF	2	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0/Q
4.437	1.462	tNET	FF	1	R12C22[3][B]	u_dvi_encoder/serdes_4b_10to1_inst/n149_s2/I0
5.469	1.032	tINS	FF	1	R12C22[3][B]	u_dvi_encoder/serdes_4b_10to1_inst/n149_s2/F
6.438	0.969	tNET	FF	1	IOB22[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[1].oddr_inst/D0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	IOB22[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[1].oddr_inst/CLK
8.478	-0.045	tSu		1	IOB22[B]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[1].oddr_inst

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.032, 26.319%; route: 2.431, 61.992%; tC2Q: 0.458, 11.689%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path21

Path Summary:

Slack	2.172
Data Arrival Time	5.951
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.325	0.863	tNET	FF	1	R11C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n82_s0/I2
5.951	0.626	tINS	FF	1	R11C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n82_s0/F
5.951	0.000	tNET	FF	1	R11C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R11C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0/CLK
8.123	-0.400	tSu		1	R11C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.725, 50.233%; route: 1.251, 36.420%; tC2Q: 0.458, 13.347%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path22

Path Summary:

Slack	2.172
Data Arrival Time	5.951
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.325	0.863	tNET	FF	1	R11C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/n81_s0/I2
5.951	0.626	tINS	FF	1	R11C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/n81_s0/F
5.951	0.000	tNET	FF	1	R11C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R11C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0/CLK
8.123	-0.400	tSu		1	R11C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.725, 50.233%; route: 1.251, 36.420%; tC2Q: 0.458, 13.347%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path23

Path Summary:

Slack	2.172
Data Arrival Time	5.951
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
5.325	0.863	tNET	FF	1	R11C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n80_s0/I2
5.951	0.626	tINS	FF	1	R11C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n80_s0/F
5.951	0.000	tNET	FF	1	R11C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R11C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0/CLK
8.123	-0.400	tSu		1	R11C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.725, 50.233%; route: 1.251, 36.420%; tC2Q: 0.458, 13.347%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path24

Path Summary:

Slack	2.184
Data Arrival Time	6.294
Data Required Time	8.478
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_0_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[2].oddr_inst
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C28[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_0_s0/CLK
2.975	0.458	tC2Q	RR	2	R11C28[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_0_s0/Q
3.395	0.420	tNET	RR	1	R12C28[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n148_s2/I0
4.021	0.626	tINS	RF	1	R12C28[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n148_s2/F
6.294	2.273	tNET	FF	1	IOB16[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[2].oddr_inst/D0

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	IOB16[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[2].oddr_inst/CLK
8.478	-0.045	tSu		1	IOB16[A]	u_dvi_encoder/serdes_4b_10to1_inst/Gowin_DDR_2/oddr_gen[2].oddr_inst

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 0.626, 16.573%; route: 2.693, 71.293%; tC2Q: 0.458, 12.134%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Path25

Path Summary:

Slack	2.304
Data Arrival Time	5.819
Data Required Time	8.123
From	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0
Launch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.517	0.244	tNET	RR	1	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK
2.975	0.458	tC2Q	RF	7	R11C29[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/Q
3.363	0.388	tNET	FF	1	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/I2
4.462	1.099	tINS	FF	30	R11C29[3][A]	u_dvi_encoder/serdes_4b_10to1_inst/n58_s0/F
4.997	0.535	tNET	FF	1	R11C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n70_s0/I2
5.819	0.822	tINS	FF	1	R11C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n70_s0/F
5.819	0.000	tNET	FF	1	R11C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.006	6.006					active clock edge time
6.006	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.523	0.244	tNET	RR	1	R11C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0/CLK
8.123	-0.400	tSu		1	R11C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	6.006
Logic Level	3
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay	cell: 1.921, 58.174%; route: 0.923, 27.946%; tC2Q: 0.458, 13.880%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.244, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-0.715
Data Arrival Time	1.773
Data Required Time	2.488
From	u_dvi_encoder/encb/dout_6_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C18[0][B]	u_dvi_encoder/encb/dout_6_s0/CLK
0.846	0.333	tC2Q	RR	3	R12C18[0][B]	u_dvi_encoder/encb/dout_6_s0/Q
1.401	0.554	tNET	RR	1	R12C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n61_s0/I1
1.773	0.372	tINS	RF	1	R12C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n61_s0/F
1.773	0.000	tNET	FF	1	R12C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R12C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0
2.488	0.000	tHld		1	R12C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_2_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 29.532%; route: 0.554, 44.006%; tC2Q: 0.333, 26.462%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path2

Path Summary:

Slack	-0.715
Data Arrival Time	1.773
Data Required Time	2.488
From	u_dvi_encoder/encb/dout_6_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C18[0][B]	u_dvi_encoder/encb/dout_6_s0/CLK
0.846	0.333	tC2Q	RR	3	R12C18[0][B]	u_dvi_encoder/encb/dout_6_s0/Q
1.401	0.554	tNET	RR	1	R12C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n60_s0/I0
1.773	0.372	tINS	RF	1	R12C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n60_s0/F
1.773	0.000	tNET	FF	1	R12C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R12C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0
2.488	0.000	tHld		1	R12C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_3_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 29.532%; route: 0.554, 44.006%; tC2Q: 0.333, 26.462%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path3

Path Summary:

Slack	-0.676
Data Arrival Time	1.812
Data Required Time	2.488
From	u_dvi_encoder/encb/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C18[0][A]	u_dvi_encoder/encb/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	5	R12C18[0][A]	u_dvi_encoder/encb/dout_7_s0/Q
1.440	0.594	tNET	RR	1	R12C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n67_s0/I1
1.812	0.372	tINS	RF	1	R12C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n67_s0/F
1.812	0.000	tNET	FF	1	R12C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R12C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0
2.488	0.000	tHld		1	R12C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_1_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 28.636%; route: 0.594, 45.705%; tC2Q: 0.333, 25.659%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path4

Path Summary:

Slack	-0.676
Data Arrival Time	1.812
Data Required Time	2.488
From	u_dvi_encoder/encb/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C18[0][A]	u_dvi_encoder/encb/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	5	R12C18[0][A]	u_dvi_encoder/encb/dout_7_s0/Q
1.440	0.594	tNET	RR	1	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n68_s0/I1
1.812	0.372	tINS	RF	1	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n68_s0/F
1.812	0.000	tNET	FF	1	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0
2.488	0.000	tHld		1	R12C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_0_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 28.636%; route: 0.594, 45.705%; tC2Q: 0.333, 25.659%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path5

Path Summary:

Slack	-0.492
Data Arrival Time	1.995
Data Required Time	2.488
From	u_dvi_encoder/encg/dout_9_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C24[0][B]	u_dvi_encoder/encg/dout_9_s0/CLK
0.846	0.333	tC2Q	RR	1	R11C24[0][B]	u_dvi_encoder/encg/dout_9_s0/Q
1.995	1.149	tNET	RR	1	R11C28[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C28[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0
2.488	0.000	tHld		1	R11C28[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_4_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.149, 77.511%; tC2Q: 0.333, 22.489%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path6

Path Summary:

Slack	-0.492
Data Arrival Time	1.995
Data Required Time	2.488
From	u_dvi_encoder/encr/dout_8_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C21[1][B]	u_dvi_encoder/encr/dout_8_s0/CLK
0.846	0.333	tC2Q	RR	1	R11C21[1][B]	u_dvi_encoder/encr/dout_8_s0/Q
1.995	1.149	tNET	RR	1	R11C25[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C25[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0
2.488	0.000	tHld		1	R11C25[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_4_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.149, 77.511%; tC2Q: 0.333, 22.489%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path7

Path Summary:

Slack	-0.492
Data Arrival Time	1.995
Data Required Time	2.488
From	u_dvi_encoder/encr/dout_9_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C21[0][B]	u_dvi_encoder/encr/dout_9_s0/CLK
0.846	0.333	tC2Q	RR	1	R11C21[0][B]	u_dvi_encoder/encr/dout_9_s0/Q
1.995	1.149	tNET	RR	1	R11C25[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C25[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0
2.488	0.000	tHld		1	R11C25[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_4_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.149, 77.511%; tC2Q: 0.333, 22.489%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path8

Path Summary:

Slack	-0.490
Data Arrival Time	1.998
Data Required Time	2.488
From	u_dvi_encoder/encb/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C18[0][A]	u_dvi_encoder/encb/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	5	R12C18[0][A]	u_dvi_encoder/encb/dout_7_s0/Q
1.442	0.595	tNET	RR	1	R12C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n65_s0/I1
1.998	0.556	tINS	RR	1	R12C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n65_s0/F
1.998	0.000	tNET	RR	1	R12C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R12C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_3_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_3_s0
2.488	0.000	tHld		1	R12C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_3_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.556, 37.453%; route: 0.595, 40.093%; tC2Q: 0.333, 22.454%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path9

Path Summary:

Slack	-0.490
Data Arrival Time	1.998
Data Required Time	2.488
From	u_dvi_encoder/encb/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C18[0][A]	u_dvi_encoder/encb/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	5	R12C18[0][A]	u_dvi_encoder/encb/dout_7_s0/Q
1.442	0.595	tNET	RR	1	R12C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n66_s0/I1
1.998	0.556	tINS	RR	1	R12C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n66_s0/F
1.998	0.000	tNET	RR	1	R12C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R12C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0
2.488	0.000	tHld		1	R12C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_2_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.556, 37.453%; route: 0.595, 40.093%; tC2Q: 0.333, 22.454%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path10

Path Summary:

Slack	-0.473
Data Arrival Time	2.014
Data Required Time	2.488
From	u_dvi_encoder/encb/dout_9_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C17[2][A]	u_dvi_encoder/encb/dout_9_s0/CLK
0.846	0.333	tC2Q	RR	1	R12C17[2][A]	u_dvi_encoder/encb/dout_9_s0/Q
2.014	1.168	tNET	RR	1	R12C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R12C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0
2.488	0.000	tHld		1	R12C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0l_4_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.168, 77.797%; tC2Q: 0.333, 22.203%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path11

Path Summary:

Slack	-0.473
Data Arrival Time	2.014
Data Required Time	2.488
From	u_dvi_encoder/encb/dout_8_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C19[0][A]	u_dvi_encoder/encb/dout_8_s0/CLK
0.846	0.333	tC2Q	RR	1	R11C19[0][A]	u_dvi_encoder/encb/dout_8_s0/Q
2.014	1.168	tNET	RR	1	R12C27[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R12C27[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0
2.488	0.000	tHld		1	R12C27[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_4_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.168, 77.797%; tC2Q: 0.333, 22.203%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path12

Path Summary:

Slack	-0.469
Data Arrival Time	2.018
Data Required Time	2.488
From	u_dvi_encoder/encr/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C21[0][A]	u_dvi_encoder/encr/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	3	R11C21[0][A]	u_dvi_encoder/encr/dout_7_s0/Q
1.646	0.800	tNET	RR	1	R11C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n85_s0/I0
2.018	0.372	tINS	RF	1	R11C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n85_s0/F
2.018	0.000	tNET	FF	1	R11C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0
2.488	0.000	tHld		1	R11C26[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_3_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 24.713%; route: 0.800, 53.142%; tC2Q: 0.333, 22.145%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path13

Path Summary:

Slack	-0.469
Data Arrival Time	2.018
Data Required Time	2.488
From	u_dvi_encoder/encr/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C21[0][A]	u_dvi_encoder/encr/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	3	R11C21[0][A]	u_dvi_encoder/encr/dout_7_s0/Q
1.646	0.800	tNET	RR	1	R11C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n86_s0/I1
2.018	0.372	tINS	RF	1	R11C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n86_s0/F
2.018	0.000	tNET	FF	1	R11C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0
2.488	0.000	tHld		1	R11C26[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 24.713%; route: 0.800, 53.142%; tC2Q: 0.333, 22.145%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path14

Path Summary:

Slack	-0.469
Data Arrival Time	2.018
Data Required Time	2.488
From	u_dvi_encoder/encr/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C21[0][A]	u_dvi_encoder/encr/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	3	R11C21[0][A]	u_dvi_encoder/encr/dout_7_s0/Q
1.646	0.800	tNET	RR	1	R11C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n87_s0/I1
2.018	0.372	tINS	RF	1	R11C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n87_s0/F
2.018	0.000	tNET	FF	1	R11C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0
2.488	0.000	tHld		1	R11C26[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 24.713%; route: 0.800, 53.142%; tC2Q: 0.333, 22.145%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path15

Path Summary:

Slack	-0.422
Data Arrival Time	2.066
Data Required Time	2.488
From	u_dvi_encoder/encg/dout_8_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C24[1][B]	u_dvi_encoder/encg/dout_8_s0/CLK
0.846	0.333	tC2Q	RR	1	R11C24[1][B]	u_dvi_encoder/encg/dout_8_s0/Q
2.066	1.219	tNET	RR	1	R11C28[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C28[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0
2.488	0.000	tHld		1	R11C28[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_4_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.219, 78.529%; tC2Q: 0.333, 21.471%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path16

Path Summary:

Slack	-0.365
Data Arrival Time	2.123
Data Required Time	2.488
From	u_dvi_encoder/encb/dout_6_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_1_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C18[0][B]	u_dvi_encoder/encb/dout_6_s0/CLK
0.846	0.333	tC2Q	RR	3	R12C18[0][B]	u_dvi_encoder/encb/dout_6_s0/Q
1.397	0.551	tNET	RR	1	R12C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n62_s0/I1
2.123	0.726	tINS	RR	1	R12C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n62_s0/F
2.123	0.000	tNET	RR	1	R12C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R12C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_1_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_1_s0
2.488	0.000	tHld		1	R12C26[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_1_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.726, 45.096%; route: 0.551, 34.199%; tC2Q: 0.333, 20.705%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path17

Path Summary:

Slack	-0.342
Data Arrival Time	2.145
Data Required Time	2.488
From	u_dvi_encoder/encg/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C24[0][A]	u_dvi_encoder/encg/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	5	R11C24[0][A]	u_dvi_encoder/encg/dout_7_s0/Q
1.419	0.573	tNET	RR	1	R11C27[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n75_s0/I1
2.145	0.726	tINS	RR	1	R11C27[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/n75_s0/F
2.145	0.000	tNET	RR	1	R11C27[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C27[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_3_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_3_s0
2.488	0.000	tHld		1	R11C27[0][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_3_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.726, 44.475%; route: 0.573, 35.104%; tC2Q: 0.333, 20.420%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path18

Path Summary:

Slack	-0.339
Data Arrival Time	2.148
Data Required Time	2.488
From	u_dvi_encoder/encg/dout_6_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_2_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C24[1][A]	u_dvi_encoder/encg/dout_6_s0/CLK
0.846	0.333	tC2Q	RR	3	R11C24[1][A]	u_dvi_encoder/encg/dout_6_s0/Q
1.424	0.578	tNET	RR	1	R11C27[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/n71_s0/I1
2.148	0.724	tINS	RR	1	R11C27[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/n71_s0/F
2.148	0.000	tNET	RR	1	R11C27[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C27[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_2_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_2_s0
2.488	0.000	tHld		1	R11C27[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_2_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 44.275%; route: 0.578, 35.340%; tC2Q: 0.333, 20.385%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path19

Path Summary:

Slack	-0.339
Data Arrival Time	2.148
Data Required Time	2.488
From	u_dvi_encoder/encg/dout_6_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C24[1][A]	u_dvi_encoder/encg/dout_6_s0/CLK
0.846	0.333	tC2Q	RR	3	R11C24[1][A]	u_dvi_encoder/encg/dout_6_s0/Q
1.424	0.578	tNET	RR	1	R11C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n70_s0/I0
2.148	0.724	tINS	RR	1	R11C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/n70_s0/F
2.148	0.000	tNET	RR	1	R11C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0
2.488	0.000	tHld		1	R11C27[2][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_3_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 44.275%; route: 0.578, 35.340%; tC2Q: 0.333, 20.385%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path20

Path Summary:

Slack	-0.337
Data Arrival Time	2.151
Data Required Time	2.488
From	u_dvi_encoder/encg/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_2_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C24[0][A]	u_dvi_encoder/encg/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	5	R11C24[0][A]	u_dvi_encoder/encg/dout_7_s0/Q
1.427	0.581	tNET	RR	1	R11C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n76_s0/I1
2.151	0.724	tINS	RR	1	R11C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n76_s0/F
2.151	0.000	tNET	RR	1	R11C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_2_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_2_s0
2.488	0.000	tHld		1	R11C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_2_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 44.204%; route: 0.581, 35.444%; tC2Q: 0.333, 20.352%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path21

Path Summary:

Slack	-0.337
Data Arrival Time	2.151
Data Required Time	2.488
From	u_dvi_encoder/encg/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C24[0][A]	u_dvi_encoder/encg/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	5	R11C24[0][A]	u_dvi_encoder/encg/dout_7_s0/Q
1.427	0.581	tNET	RR	1	R11C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n77_s0/I1
2.151	0.724	tINS	RR	1	R11C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/n77_s0/F
2.151	0.000	tNET	RR	1	R11C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0
2.488	0.000	tHld		1	R11C27[1][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_1_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 44.204%; route: 0.581, 35.444%; tC2Q: 0.333, 20.352%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path22

Path Summary:

Slack	-0.337
Data Arrival Time	2.151
Data Required Time	2.488
From	u_dvi_encoder/encg/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C24[0][A]	u_dvi_encoder/encg/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	5	R11C24[0][A]	u_dvi_encoder/encg/dout_7_s0/Q
1.427	0.581	tNET	RR	1	R11C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n78_s0/I1
2.151	0.724	tINS	RR	1	R11C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/n78_s0/F
2.151	0.000	tNET	RR	1	R11C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0
2.488	0.000	tHld		1	R11C27[1][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1l_0_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 44.204%; route: 0.581, 35.444%; tC2Q: 0.333, 20.352%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path23

Path Summary:

Slack	-0.320
Data Arrival Time	2.168
Data Required Time	2.488
From	u_dvi_encoder/encb/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C18[0][A]	u_dvi_encoder/encb/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	5	R12C18[0][A]	u_dvi_encoder/encb/dout_7_s0/Q
1.442	0.595	tNET	RR	1	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/n63_s0/I0
2.168	0.726	tINS	RR	1	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/n63_s0/F
2.168	0.000	tNET	RR	1	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0
2.488	0.000	tHld		1	R12C26[2][A]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_0h_0_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.726, 43.880%; route: 0.595, 35.974%; tC2Q: 0.333, 20.147%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path24

Path Summary:

Slack	-0.250
Data Arrival Time	2.238
Data Required Time	2.488
From	u_dvi_encoder/encg/dout_7_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C24[0][A]	u_dvi_encoder/encg/dout_7_s0/CLK
0.846	0.333	tC2Q	RR	5	R11C24[0][A]	u_dvi_encoder/encg/dout_7_s0/Q
1.682	0.835	tNET	RR	1	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n73_s0/I0
2.238	0.556	tINS	RR	1	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n73_s0/F
2.238	0.000	tNET	RR	1	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0
2.488	0.000	tHld		1	R12C27[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_1h_0_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.556, 32.238%; route: 0.835, 48.434%; tC2Q: 0.333, 19.328%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Path25

Path Summary:

Slack	-0.250
Data Arrival Time	2.238
Data Required Time	2.488
From	u_dvi_encoder/encr/dout_6_s0
To	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	66	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C21[1][A]	u_dvi_encoder/encr/dout_6_s0/CLK
0.846	0.333	tC2Q	RR	3	R11C21[1][A]	u_dvi_encoder/encr/dout_6_s0/Q
1.682	0.836	tNET	RR	1	R11C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n80_s0/I0
2.238	0.556	tINS	RR	1	R11C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/n80_s0/F
2.238	0.000	tNET	RR	1	R11C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	50	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.458	0.185	tNET	RR	1	R11C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0/CLK
2.488	0.030	tUnc				u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0
2.488	0.000	tHld		1	R11C26[0][B]	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2h_3_s0

Path Statistics:

Clock Skew	1.945
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.556, 32.233%; route: 0.836, 48.442%; tC2Q: 0.333, 19.324%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.185, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	1.675
Actual Width:	2.925
Required Width:	1.250
Type:	Low Pulse Width
Clock:	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
Objects:	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.003	0.000			active clock edge time
3.003	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
5.276	2.273	tCL	FF	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
5.539	0.262	tNET	FF	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.006	0.000			active clock edge time
6.006	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.464	0.185	tNET	RR	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_1_s0/CLK

MPW2

MPW Summary:

Slack:	1.675
Actual Width:	2.925
Required Width:	1.250
Type:	Low Pulse Width
Clock:	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
Objects:	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.003	0.000			active clock edge time
3.003	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
5.276	2.273	tCL	FF	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
5.539	0.262	tNET	FF	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.006	0.000			active clock edge time
6.006	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.464	0.185	tNET	RR	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_2_s0/CLK

MPW3

MPW Summary:

Slack:	1.675
Actual Width:	2.925
Required Width:	1.250
Type:	Low Pulse Width
Clock:	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
Objects:	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.003	0.000			active clock edge time
3.003	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
5.276	2.273	tCL	FF	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
5.539	0.262	tNET	FF	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.006	0.000			active clock edge time
6.006	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.464	0.185	tNET	RR	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_1_s0/CLK

MPW4

MPW Summary:

Slack:	1.675
Actual Width:	2.925
Required Width:	1.250
Type:	Low Pulse Width
Clock:	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
Objects:	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.003	0.000			active clock edge time
3.003	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
5.276	2.273	tCL	FF	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
5.539	0.262	tNET	FF	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.006	0.000			active clock edge time
6.006	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.464	0.185	tNET	RR	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_0_s0/CLK

MPW5

MPW Summary:

Slack:	1.675
Actual Width:	2.925
Required Width:	1.250
Type:	Low Pulse Width
Clock:	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
Objects:	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.003	0.000			active clock edge time
3.003	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
5.276	2.273	tCL	FF	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
5.539	0.262	tNET	FF	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.006	0.000			active clock edge time
6.006	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.464	0.185	tNET	RR	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_mod5_2_s0/CLK

MPW6

MPW Summary:

Slack:	1.675
Actual Width:	2.925
Required Width:	1.250
Type:	Low Pulse Width
Clock:	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
Objects:	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_2_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.003	0.000			active clock edge time
3.003	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
5.276	2.273	tCL	FF	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
5.539	0.262	tNET	FF	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_2_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.006	0.000			active clock edge time
6.006	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.464	0.185	tNET	RR	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_2_s1/CLK

MPW7

MPW Summary:

Slack:	1.675
Actual Width:	2.925
Required Width:	1.250
Type:	Low Pulse Width
Clock:	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
Objects:	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_3_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.003	0.000			active clock edge time
3.003	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
5.276	2.273	tCL	FF	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
5.539	0.262	tNET	FF	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_3_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.006	0.000			active clock edge time
6.006	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.464	0.185	tNET	RR	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3l_3_s1/CLK

MPW8

MPW Summary:

Slack:	1.675
Actual Width:	2.925
Required Width:	1.250
Type:	Low Pulse Width
Clock:	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
Objects:	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.003	0.000			active clock edge time
3.003	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
5.276	2.273	tCL	FF	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
5.539	0.262	tNET	FF	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.006	0.000			active clock edge time
6.006	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.464	0.185	tNET	RR	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_2l_0_s0/CLK

MPW9

MPW Summary:

Slack:	1.675
Actual Width:	2.925
Required Width:	1.250
Type:	Low Pulse Width
Clock:	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
Objects:	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.003	0.000			active clock edge time
3.003	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
5.276	2.273	tCL	FF	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
5.539	0.262	tNET	FF	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.006	0.000			active clock edge time
6.006	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.464	0.185	tNET	RR	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_2_s0/CLK

MPW10

MPW Summary:

Slack:	1.675
Actual Width:	2.925
Required Width:	1.250
Type:	Low Pulse Width
Clock:	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
Objects:	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
3.003	0.000			active clock edge time
3.003	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
5.276	2.273	tCL	FF	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
5.539	0.262	tNET	FF	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
6.006	0.000			active clock edge time
6.006	0.000			Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.279	2.273	tCL	RR	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
8.464	0.185	tNET	RR	u_dvi_encoder/serdes_4b_10to1_inst/TMDS_shift_3h_0_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
66	clk_vga	4.660	0.257
50	clk_vgax5	0.242	0.376
30	n58_3	1.237	1.361
27	de_reg[1]	25.256	1.832
20	hcount_ov	24.127	0.852
12	vcount_r[9]	21.681	1.349
11	vcount_r[5]	20.466	1.809
10	n0q_m[3]	22.565	0.836
10	n0q_m[3]	23.653	1.334
10	vcount_r[4]	18.004	1.984

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R12C15	84.72%
R12C16	83.33%
R12C27	79.17%
R11C28	77.78%
R11C26	76.39%
R12C26	75.00%
R11C27	73.61%
R11C29	70.83%
R11C15	66.67%
R11C21	65.28%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk_osc -period 37.037 -waveform {0 18.518} [get_ports {clk}]